Yosuke Ueno

Orcid: 0000-0002-0402-9914

According to our database1, Yosuke Ueno authored at least 11 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
C3-VQA: Cryogenic Counter-based Co-processor for Variational Quantum Algorithms.
CoRR, 2024

SFQ counter-based precomputation for large-scale cryogenic VQE machines.
CoRR, 2024

Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines.
IEEE Comput. Archit. Lett., 2024

2023
Circuit designs for practical-scale fault-tolerant quantum computing.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
NEO-QEC: Neural Network Enhanced Online Superconducting Decoder for Surface Codes.
CoRR, 2022

QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021
Path Planning and Moving Obstacle Avoidance with Neuromorphic Computing.
Proceedings of the IEEE International Conference on Intelligence and Safety for Robotics, 2021

QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2016
A 12 Gb/s 0.9 mW/Gb/s Wide-Bandwidth Injection-Type CDR in 28 nm CMOS With Reference-Free Frequency Capture.
IEEE J. Solid State Circuits, 2016

10.4 A 12Gb/s 0.9mW/Gb/s wide-bandwidth injection-type CDR in 28nm CMOS with reference-free frequency capture.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016


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