Yosuke Toyama

According to our database, Yosuke Toyama authored at least 6 papers between 2013 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators.

Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Shigeru Maya, Akihide Sai, Kohei Onizuka

IEEE J. Solid State Circuits, 2019

2018

PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators.

Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications.

Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Akihide Sai, Kohei Onizuka

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2016

A programmable ΔΣ SAR-ADC with charge shuttling technique.

Kohei Yamada, Yosuke Toyama, Hiroki Ishikuro

Proceedings of the International SoC Design Conference, 2016

20 mV input, 4.2 V output SIDO boost converter with low-power controller and adaptive switch size selector for thermoelectric energy harvesting.

Yosuke Toyama, Taichi Ogawa, Takeshi Ueno, Tetsuro Itakura

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2013

A voltage scaling 0.25-1.8 V delta-sigma modulator with inverter-opamp self-configuring amplifier.

Kentaro Yoshioka, Yosuke Toyama, Teruo Jyo, Hiroki Ishikuro

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013