Yosuke Terachi

According to our database, Yosuke Terachi authored at least 5 papers between 2010 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

An FPGA Implementation of a HOG-based Object Detection Processor.

Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

IPSJ Trans. Syst. LSI Des. Methodol., 2013

A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video.

Kosuke Mizuno, Kenta Takagi, Yosuke Terachi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2013

2012

Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection.

Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

2011

A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition.

Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2011

2010

Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video.

Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010