Yosuke Ogasawara
According to our database1,
Yosuke Ogasawara
authored at least 12 papers
between 2008 and 2018.
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Bibliography
2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 15mW -105dBm Image-Sparse-Sliding-IF Receiver with Transformer-Based on-Chip Q-Enhanced RF Matching Network for a 113dB-Link-Budget BLE 5.0 TRX.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2017
IEICE Trans. Electron., 2017
An 18 µW Spur Cancelled Clock Generator for Recovering Receiver Sensitivity in Wireless SoCs.
IEICE Trans. Electron., 2017
2016
An 18 µW spur canceled clock generator for recovering receiver sensitivity in wireless SoCs.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2012
A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
2011
IEICE Trans. Electron., 2011
2010
A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010
A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
A single-chip 8-band CMOS transceiver for W-CDMA(HSPA) / GSM(GPRS) / EDGE with digital interface.
Proceedings of the ESSCIRC 2008, 2008