Yosuke Kato
According to our database1,
Yosuke Kato
authored at least 11 papers
between 2002 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
IEEE J. Solid State Circuits, 2023
2022
A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2019
A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2013
A 19 nm 112.8 mm<sup>2</sup> 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface.
IEEE J. Solid State Circuits, 2013
2012
IEEE J. Solid State Circuits, 2012
A 19nm 112.8mm<sup>2</sup> 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2004
Proceedings of the Ninth International Workshop on Frontiers in Handwriting Recognition, 2004
2002
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002