Yossi Lev

Orcid: 0000-0003-3514-8016

According to our database1, Yossi Lev authored at least 27 papers between 2004 and 2022.

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Bibliography

2022
BQ: A Lock-Free Queue with Batching.
ACM Trans. Parallel Comput., 2022

2017
Transactional Lock Elision Meets Combining.
Proceedings of the ACM Symposium on Principles of Distributed Computing, 2017

2016
Investigating the Performance of Hardware Transactions on a Multi-Socket Machine.
Proceedings of the 28th ACM Symposium on Parallelism in Algorithms and Architectures, 2016

Refined transactional lock elision.
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016

2015
The Influence of Malloc Placement on TSX Hardware Transactional Memory.
CoRR, 2015

2014
Hardware extensions to make lazy subscription safe.
CoRR, 2014

Adaptive integration of hardware and software lock elision techniques.
Proceedings of the 26th ACM Symposium on Parallelism in Algorithms and Architectures, 2014

2013
Scalable statistics counters.
Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures, 2013

Using hardware transactional memory to correct and simplify and readers-writer lock algorithm.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2013

NUMA-aware reader-writer locks.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2013

Constrained Data-Driven Parallelism.
Proceedings of the 5th USENIX Workshop on Hot Topics in Parallelism, 2013

2011
On the power of hardware transactional memory to simplify memory management.
Proceedings of the 30th Annual ACM Symposium on Principles of Distributed Computing, 2011

Lightweight parallel accumulators using C++ templates.
Proceedings of the 4th International Workshop on Multicore Software Engineering, 2011

Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory.
Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, 2011

2010
Debugging and Profiling of Transactional Programs.
PhD thesis, 2010

Simplifying concurrent algorithms by exploiting hardware transactional memory.
Proceedings of the SPAA 2010: Proceedings of the 22nd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2010

2009
Scalable reader-writer locks.
Proceedings of the SPAA 2009: Proceedings of the 21st Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2009

Early experience with a commercial hardware transactional memory implementation.
Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009

tm_db: A Generic Debugging Library for Transactional Programs.
Proceedings of the PACT 2009, 2009

2008
Surface and deep learning processes in distance education: Synchronous versus asynchronous systems.
Comput. Educ., 2008

Split hardware transactions: true nesting of transactions using best-effort hardware transactional memory.
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008

2007
A Simple Optimistic Skiplist Algorithm.
Proceedings of the Structural Information and Communication Complexity, 2007

SNZI: scalable NonZero indicators.
Proceedings of the Twenty-Sixth Annual ACM Symposium on Principles of Distributed Computing, 2007

2006
A dynamic-sized nonblocking work stealing deque.
Distributed Comput., 2006

Hybrid transactional memory.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005
Dynamic circular work-stealing deque.
Proceedings of the SPAA 2005: Proceedings of the 17th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2005

2004
Dynamic Memory ABP Work-Stealing.
Proceedings of the Distributed Computing, 18th International Conference, 2004


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