Yoshiyasu Ogasawara

According to our database, Yoshiyasu Ogasawara authored at least 9 papers between 2005 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2009

An Effective Replacement Strategy of Cache Memory for an SMT Processor.

Yoshiyasu Ogasawara, Hironori Nakajo

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor.

Yoshiyasu Ogasawara, Pulung Waskito, Shinobu Miwa, Hironori Nakajo

Proceedings of the 2009 International Conference on Computer Design, 2009

2007

A two-layered approach to communicative artifacts.

Yong Xu, Tatsuya Hiramatsu, Kateryna Tarasenko, Toyoaki Nishida, Yoshiyasu Ogasawara, Takashi Tajima, Makoto Hatakeyama, Masashi Okamoto, Yukiko I. Nakano

AI Soc., 2007

Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices.

Satoshi Watanabe, Yoshiyasu Ogasawara, Ippei Tate, Hirofumi Yano, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007

2006

Toward Robots as Embodied Knowledge Media.

Toyoaki Nishida, Kazunori Terada, Takashi Tajima, Makoto Hatakeyama, Yoshiyasu Ogasawara, Yasuyuki Sumi, Yong Xu, Yasser F. O. Mohammad, Kateryna Tarasenko, Taku Ohya, Tatsuya Hiramatsu

IEICE Trans. Inf. Syst., 2006

A Model of Implementable SMT Processor on FPGA.

Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

Towards Reconfigurable Cache Memory for a Multithreaded Processor.

Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

2005

A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation.

Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

How to Make Robot a Robust and Interactive Communicator.

Yoshiyasu Ogasawara, Masashi Okamoto, Yukiko I. Nakano, Yong Xu, Toyoaki Nishida

Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2005