Yoshisato Yokoyama
Orcid: 0000-0001-8552-4070
According to our database1,
Yoshisato Yokoyama
authored at least 11 papers
between 2014 and 2025.
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Collaborative distances:
Timeline
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2024
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2025
A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm<sup>2</sup> Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture.
IEEE J. Solid State Circuits, January, 2025
2024
15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing.
IEEE J. Solid State Circuits, 2023
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
2020
A 29.2 Mb/mm<sup>2</sup> Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2015
A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014