Yoshio Matsuda
Orcid: 0000-0003-0114-0219
According to our database1,
Yoshio Matsuda
authored at least 55 papers
between 1989 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
1990
1995
2000
2005
2010
2015
2020
0
1
2
3
4
5
6
1
1
2
2
1
3
1
2
1
4
2
1
2
1
1
1
3
2
2
3
2
4
3
2
1
1
1
1
1
1
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2022
Int. J. Hum. Comput. Interact., 2022
2020
Proceedings of the IUI '20: 25th International Conference on Intelligent User Interfaces, 2020
Proceedings of the HCI International 2020 - Late Breaking Posters, 2020
2019
A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications.
IEICE Trans. Electron., 2019
Proceedings of the 8th ACM International Symposium on Pervasive Displays, PerDis 2019, 2019
Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis.
Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019
Proceedings of the 2019 IEEE International Conference on Internet of Things and Intelligence System, 2019
2018
Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications.
IEEE Trans. Multi Scale Comput. Syst., 2018
High-Performance Super-Resolution via Patch-Based Deep Neural Network for Real-Time Implementation.
IEICE Trans. Inf. Syst., 2018
Proceedings of the 7th ACM International Symposium on Pervasive Displays, 2018
Ultra-low-latency Video Coding Method for Autonomous Vehicles and Virtual Reality Devices.
Proceedings of the IEEE International Conference on Internet of Things and Intelligence System, 2018
2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
2016
A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016
2015
A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table.
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015
A fast atom selection method based on the order of initial inner product values for image denoising using sparse representation.
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015
A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
2014
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current.
J. Circuits Syst. Comput., 2014
A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
The LSI implementation of a memory based field programmable device for MCU peripherals.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
2013
Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.
Proceedings of the International Symposium on Quality Electronic Design, 2013
2012
General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield.
IET Circuits Devices Syst., 2012
Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
2011
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Proceedings of the 2011 IEEE International Conference on Signal and Image Processing Applications, 2011
2010
Adiabatic charging and discharging method with minimum energy dissipation for a variable-gap capacitor system.
IET Circuits Devices Syst., 2010
IEICE Trans. Inf. Syst., 2010
A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications.
IEICE Trans. Electron., 2010
Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation.
IEICE Electron. Express, 2010
Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Adiabatic SRAM with a Large Margin of VT Variation by Controlling the Cell-power-line and Word-line Voltage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
IEICE Trans. Electron., 2008
A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
2000
IEEE J. Solid State Circuits, 2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
IEEE J. Solid State Circuits, 1999
1997
IEEE J. Sel. Areas Commun., 1997
1996
IEEE J. Solid State Circuits, 1996
1994
Proceedings of the Proceedings IEEE INFOCOM '94, 1994
1993
IEEE J. Solid State Circuits, July, 1993
1990
IEEE J. Solid State Circuits, February, 1990
IEEE J. Solid State Circuits, February, 1990
1989
IEEE J. Solid State Circuits, October, 1989
IEEE J. Solid State Circuits, February, 1989
Proceedings of the Proceedings International Test Conference 1989, 1989