Yoshinori Nishi
Orcid: 0000-0002-7178-5816
According to our database1,
Yoshinori Nishi
authored at least 6 papers
between 2006 and 2024.
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Collaborative distances:
Timeline
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2024
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2024
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.
IEEE J. Solid State Circuits, April, 2024
Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS.
IEEE J. Solid State Circuits, 2023
2022
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2010
Passive and Active Reduction Techniques for On-Chip High-Frequency Digital Power Supply Noise.
IEEE Trans. Very Large Scale Integr. Syst., 2010
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006