Yoshinobu Yamagami

According to our database, Yoshinobu Yamagami authored at least 9 papers between 2004 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses.

Toshikazu Suzuki, Hiroyuki Yamauchi, Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu

IEEE J. Solid State Circuits, 2008

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara

IEEE J. Solid State Circuits, 2008

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues.

Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu

IEEE J. Solid State Circuits, 2008

2007

A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses.

Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami

IEICE Trans. Electron., 2007

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations.

Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme.

Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi

IEEE J. Solid State Circuits, 2006

A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (<i>V</i>_th) Variation.

Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami

IEICE Trans. Electron., 2006

2005

0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier.

Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi

IEICE Trans. Electron., 2005

2004

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications.

Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade

IEEE J. Solid State Circuits, 2004