Yoshinobu Nakagome

According to our database1, Yoshinobu Nakagome authored at least 21 papers between 1988 and 2004.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2011, "For pioneering development of low-voltage dynamic random access memory circuits and low-leakage complementary metal-oxide semiconductor circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2004
Introduction to the Special Issue.
IEEE J. Solid State Circuits, 2004

2003
Guest Editorial.
IEEE J. Solid State Circuits, 2003

Review and future prospects of low-voltage RAM circuits.
IBM J. Res. Dev., 2003

1999
A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM.
IEEE J. Solid State Circuits, 1999

1997
A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip.
IEEE J. Solid State Circuits, 1997

Limitations and challenges of multigigabit DRAM chip design.
IEEE J. Solid State Circuits, 1997

1995
Low-noise, high-speed data transmission using a ringing-canceling output buffer.
IEEE J. Solid State Circuits, December, 1995

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.
IEEE J. Solid State Circuits, November, 1995

A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits.
IEEE J. Solid State Circuits, April, 1995

A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer.
IEEE J. Solid State Circuits, March, 1995

Trends in low-power RAM circuit technologies.
Proc. IEEE, 1995

1994
Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs.
IEEE J. Solid State Circuits, April, 1994

1993
A 1.5-ns 32-b CMOS ALU in double pass-transistor logic.
IEEE J. Solid State Circuits, November, 1993

Sub-1-V swing internal bus architecture for future low-power ULSIs.
IEEE J. Solid State Circuits, April, 1993

1992
An experimental single-chip data flow CPU.
IEEE J. Solid State Circuits, January, 1992

1991
A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's.
IEEE J. Solid State Circuits, November, 1991

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM.
IEEE J. Solid State Circuits, July, 1991

An experimental 1.5-V 64-Mb DRAM.
IEEE J. Solid State Circuits, April, 1991

1990
An on-chip smart memory for a data-flow CPU.
IEEE J. Solid State Circuits, February, 1990

1989
New DRAM noise generation under half-V<sub>cc</sub> precharge and its reduction using a transposed amplifier.
IEEE J. Solid State Circuits, August, 1989

1988
An experimental large-capacity semiconductor file memory using 16-levels/cell storage.
IEEE J. Solid State Circuits, February, 1988


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