Yoshinobu Higami

According to our database, Yoshinobu Higami authored at least 92 papers between 1994 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Testing and Delay-Monitoring for the High Reliability of Memory-Based Programmable Logic Device.

Xihong Zhou, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi

IEICE Trans. Inf. Syst., January, 2024

Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs.

Senling Wang, Shaoqi Wei, Hisashi Okamoto, Tatusya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Ruijun Ma, Tianming Ni, Hiroshi Takahashi, Xiaoqing Wen

Proceedings of the IEEE International Test Conference in Asia, 2024

2023

Test Point Insertion for Multi-Cycle Power-On Self-Test.

Senling Wang, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima

ACM Trans. Design Autom. Electr. Syst., 2023

SASL-JTAG: A Light-Weight Dependable JTAG.

Senling Wang, Shaoqi Wei, Jun Ma, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Akihiro Shimizu, Xiaoqing Wen, Tianming Ni

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022

Preliminary Study on Noise-Resilient Artificial Neural Networks for On-Chip Test Generation.

Tsutomu Inamoto, Tomoki Nishino, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi

Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2020

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST.

Hanan T. Al-Awadhi, Tomoki Aono, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima

IEICE Trans. Inf. Syst., 2020

Formulation of a Test Pattern Measure That Counts Distinguished Fault-Pairs for Circuit Fault Diagnosis.

Tsutomu Inamoto, Yoshinobu Higami

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

2018

Evaluation of educational applications in terms of communication delay between tablets with Bluetooth or Wi-Fi Direct.

Keiichi Endo, Gakuto Fujioka, Ayame Onoyama, Dai Okano, Yoshinobu Higami, Shinya Kobayashi

Vietnam. J. Comput. Sci., 2018

Automotive Functional Safety Assurance by POST with Sequential Observation.

Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima

IEEE Des. Test, 2018

Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262.

Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima

Proceedings of the 23rd IEEE European Test Symposium, 2018

Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST.

Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines.

Hiroyuki Yotsuyanagi, Kotaro Ise, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Trip-Based Integer Linear Programming Model for Static Multi-Car Elevator Operation Problems.

Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line.

Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja

IEICE Trans. Inf. Syst., 2017

On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects.

Yuuya Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi

Proceedings of the 17th International Symposium on Communications and Information Technologies, 2017

Harnessing Fuzziness of the Pragmatic Rule-Design Without IF-THEN Rules.

Tsutomu Inamoto, Yoshinobu Higami

Proceedings of the Fuzzy Systems and Data Mining III, 2017

Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD).

Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Masayuki Sato, Mitsunori Katsu, Shoichi Sekiguchi

Proceedings of the 26th IEEE Asian Test Symposium, 2017

Comparative Evaluation of Bluetooth and Wi-Fi Direct for Tablet-Oriented Educational Applications.

Keiichi Endo, Ayame Onoyama, Dai Okano, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the Intelligent Information and Database Systems - 9th Asian Conference, 2017

2016

Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays.

Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja

IPSJ Trans. Syst. LSI Des. Methodol., 2016

Road-Map to Bridge Theoretical and Practical Approaches for Elevator Operations.

Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the 5th IIAI International Congress on Advanced Applied Informatics, 2016

Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation.

Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima

Proceedings of the 25th IEEE Asian Test Symposium, 2016

Evaluation of Influence Exerted by a Malicious Group's Various Aims in the External Grid.

Kosuke Yamaguchi, Tsutomu Inamoto, Keiichi Endo, Yoshinobu Higami, Shinya Kobayashi

Proceedings of the Hard and Soft Computing for Artificial Intelligence, 2016

Design and Implementation of Data Synchronization and Offline Capabilities in Native Mobile Apps.

Kamoliddin Mavlonov, Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the Intelligent Information and Database Systems - 8th Asian Conference, 2016

2015

Diagnosis of Delay Faults Considering Hazards.

Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Giving formal roles to elevators for breaking symmetry in static elevator operation problems.

Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

2014

Optimal Periods for Probing Convergence of Infinite-stage Dynamic Programmings on GPUs.

Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi

Int. J. Netw. Comput., 2014

A call-based integer programming model for static elevator operation problems.

Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the 2014 Joint 7th International Conference on Soft Computing and Intelligent Systems (SCIS) and 15th International Symposium on Advanced Intelligent Systems (ISIS), 2014

Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults.

Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Decreasing computational times for solving static elevator operation problems by assuming maximum waiting times.

Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

Sushi: A Lightweight Distributed Image Storage System for Mobile and Web Services.

Kamoliddin Mavlonov, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the Soft Computing in Computer and Information Science, 2014

2013

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment.

Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja

IEICE Trans. Inf. Syst., 2013

Intermittently Proving Dynamic Programming to Solve Infinite MDPs on GPUs.

Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the First International Symposium on Computing and Networking, 2013

Injecting speculation on ideal trajectories into a trip-based integer programming model for elevator operations.

Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

Diagnosing Resistive Open Faults Using Small Delay Fault Simulation.

Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hironobu Yotsuyanagi, Masaki Hashizume, Kewal K. Saluja

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Dynamic Routing and Wavelength Assignment with Backward Reservation in Wavelength-routed Multifiber WDM Networks.

Dewiani, Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi

J. Networks, 2012

Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool.

Yoshinobu Higami, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo

IEICE Trans. Inf. Syst., 2012

Diagnosis for Bridging Faults on Clock Lines.

Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja

Proceedings of the IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012

Dynamic routing and wavelength assignment in multifiber WDM networks with sparse wavelength conversion.

Dewiani, Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the International Conference on Information and Communication Technology Convergence, 2012

2011

Enhancement of Clock Delay Faults Testing.

Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja

Proceedings of the 16th European Test Symposium, 2011

On Detecting Transition Faults in the Presence of Clock Delay Faults.

Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Test Pattern Selection for Defect-Aware Test.

Yoshinobu Higami, Hiroshi Furutani, Takao Sakai, Shuichi Kameyama, Hiroshi Takahashi

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Fault simulation and test generation for clock delay faults.

Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Replica Selection and Downloading based on Wavelength Availability in λ-grid Networks.

Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi

J. Commun., 2010

Dynamic Parallel Downloading with Network Coding in $\lambda$-Grid Networks.

Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi

J. Commun., 2010

2009

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation.

Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu

IPSJ Trans. Syst. LSI Des. Methodol., 2009

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation.

Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu

Inf. Media Technol., 2009

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects.

Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.

Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A Novel Approach for Improving the Quality of Open Fault Diagnosis.

Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Diagnostic test generation for transition faults using a stuck-at ATPG tool.

Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu

Proceedings of the 2009 IEEE International Test Conference, 2009

New Class of Tests for Open Faults with Considering Adjacent Lines.

Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information.

Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Koji Yamazaki

IEICE Trans. Inf. Syst., 2008

Post-BIST Fault Diagnosis for Multiple Faults.

Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato

IEICE Trans. Inf. Syst., 2008

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors.

Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools.

Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu

IEICE Trans. Inf. Syst., 2008

Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults.

Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation.

Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines.

Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Timing-Aware Diagnosis for Small Delay Defects.

Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines.

Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the 16th Asian Test Symposium, 2007

Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator.

Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu

Proceedings of the 16th Asian Test Symposium, 2007

Reliability of Node Information on Autonomous Load Distribution Method.

Michihiko Kudo, Koichi Kashiwagi, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the Advances in Information Processing and Protection., 2007

Development of Concealing the Purpose of Processing for Programs in a Distributed Computing Environment.

Yuji Kinoshita, Koichi Kashiwagi, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the Advances in Information Processing and Protection., 2007

A Consideration of Processor Utilization on Multi-Processor System.

Koichi Kashiwagi, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the Advances in Information Processing and Protection., 2007

2006

On Finding Don't Cares in Test Sequences for Sequential Circuits.

Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu

IEICE Trans. Inf. Syst., 2006

Effective Post-BIST Fault Diagnosis for Multiple Faults.

Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Diagnosis of Transistor Shorts in Logic Test Environment.

Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu

Proceedings of the 15th Asian Test Symposium, 2006

Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits.

Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Test cost reduction for logic circuits: Reduction of test data volume and test application time.

Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu

Syst. Comput. Jpn., 2005

On the fault diagnosis in the presence of unknown fault models using pass/fail information.

T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Improvement of the processors operating ratio in task scheduling using the deadline method.

Koichi Kashiwagi, Yoshinobu Higami, Shin-ya Kobayashi

Proceedings of the Enhanced Methods in Computer Security, 2005

2004

Generation of Test Sequences with Low Power Dissipation for Sequential Circuits.

Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu

IEICE Trans. Inf. Syst., 2004

Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set.

Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests.

Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction.

Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

A Method to Find Don't Care Values in Test Sequences for Sequential Circuits.

Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002

Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits.

Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

A Method to Reduce Power Dissipation during Test for Sequential Circuits.

Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits.

Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Test Generation for Double Stuck-at Faults.

Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Static test compaction for IDDQ testing of bridging faults in sequential circuits.

Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita

Syst. Comput. Jpn., 2000

Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.

Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita

J. Electron. Test., 2000

Test sequence compaction for sequential circuits with reset states.

Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Fault models and test generation for IDDQ testing: embedded tutorial.

Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita

Proceedings of ASP-DAC 2000, 2000

1999

Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits.

Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.

Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits.

Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Design of partially parallel scan chain.

Yoshinobu Higami, Kozo Kinoshita

Proceedings of the European Design and Test Conference, 1997

1996

Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique.

Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Partial scan design and test sequence generation based on reduced scan shift method.

Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita

J. Electron. Test., 1995

Test sequence compaction by reduced scan shift and retiming.

Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

Reduced Scan Shift: A New Testing Method for Sequential Circuit.

Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994