Yoshikazu Morooka

According to our database1, Yoshikazu Morooka authored at least 8 papers between 1985 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test.
IEICE Trans. Electron., 2009

2007
A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

1999
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface.
IEEE J. Solid State Circuits, 1999

1996
A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory.
IEEE J. Solid State Circuits, 1996

1994
An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs.
IEEE J. Solid State Circuits, April, 1994

An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM.
IEEE J. Solid State Circuits, March, 1994

1991
An Address Maskable Parallel Testing for Ultra High Density DRAMs.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1985
Test Pattern Considerations for Fault Tolerant High Density DRAM.
Proceedings of the Proceedings International Test Conference 1985, 1985


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