Yoshikazu Miyawaki

According to our database, Yoshikazu Miyawaki authored at least 4 papers between 1989 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1999

A 29-mm², 1.8-V-only, 16-Mb DINOR flash memory with gate-protected-poly-diode (GPPD) charge pump.

Yoshikazu Miyawaki, Osamu Ishizaki, Yoshihiko Okihara, Tsutomu Inaba, Fumihiko Nitta, Masaaki Mihara, Takashi Hayasaka, Kazuo Kobayashi, Tadashi Omae, Hiroshi Kimura, Satoshi Shimizu, Hiromi Makimoto, Yoshiki Kawajiri, Masashi Wada, Hirofumi Sonoyama, Jun Etoh

IEEE J. Solid State Circuits, 1999

1994

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.

Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara

IEEE J. Solid State Circuits, April, 1994

1989

120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs.

Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

IEEE J. Solid State Circuits, October, 1989

A 5 V only one-transistor 256 K EEPROM with page-mode erase.

Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

IEEE J. Solid State Circuits, August, 1989