Yoshikazu Kiyoshige

According to our database, Yoshikazu Kiyoshige authored at least 4 papers between 2001 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.

Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

IEICE Trans. Electron., 2011

2010

A 45nm 37.3GOPS/W heterogeneous multi-core SoC.

Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2002

Application of High-Quality Built-In Test to Industrial Designs.

Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Test Generation for Multiple-Threshold Gate-Delay Fault Model.

Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001