Yoshikatsu Ryu
According to our database1,
Yoshikatsu Ryu
authored at least 14 papers
between 2010 and 2014.
Collaborative distances:
Collaborative distances:
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Bibliography
2014
IEEE J. Solid State Circuits, 2014
2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection.
IEEE J. Solid State Circuits, 2012
Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and V<sub>TH</sub>-Tuned Oscillator With Fixed Charge Programming.
IEEE J. Solid State Circuits, 2012
A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW.
Proceedings of the Symposium on VLSI Circuits, 2012
A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage.
IEICE Trans. Electron., 2011
0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS.
IEICE Trans. Electron., 2011
0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications.
IEICE Trans. Electron., 2011
A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 80-mV input, fast startup dual-mode boost converter with charge-pumped pulse generator for energy harvesting.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010