Yoshihisa Iwata

According to our database, Yoshihisa Iwata authored at least 5 papers between 1989 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

MRAM Write Error Categorization with QCKB.

Yuui Shimizu, Hisanori Aikawa, Keiji Hosotani, Naoharu Shimomura, Tadashi Kai, Yoshihiro Ueda, Yoshiaki Asao, Yoshihisa Iwata, Kenji Tsuchida, Sumio Ikegawa

Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

A 16Mb MRAM with FORK Wiring Scheme and Burst Modes.

Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2002

Memory design using a one-transistor gain cell on SOI.

Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi

IEEE J. Solid State Circuits, 2002

1995

A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM.

Yoshihisa Iwata, Ken-ichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Hideko Oodaira, Masaki Momodomi, Yasuo Itoh, Toshiharu Watanabe, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Junichi Miyamoto

IEEE J. Solid State Circuits, November, 1995

1989

An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell.

Masaki Momodomi, Yasuo Itoh, Riichiro Shirota, Yoshihisa Iwata, Ryozo Nakayama, Ryouhei Kirisawa, Tomoharu Tanaka, Seiichi Aritome, Tetsuo Endoh, Kazunori Ohuchi, Fujjo Masuoka

IEEE J. Solid State Circuits, October, 1989