Yoshihiro Tohma

Orcid: 0000-0002-2040-6708

According to our database1, Yoshihiro Tohma authored at least 30 papers between 1964 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1980, "For, contributions to the theory and design of fault-tolerant digital systems, and to engineering education.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
The Transfer Function of Amplitude Modulation Circuits Using Varactor Diode.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

2007
Software reliability evaluation in service operation.
Syst. Comput. Jpn., 2007

2004
Incorporating Fault Tolerance into an Autonomic-Computing Environment.
IEEE Distributed Syst. Online, 2004

Current research activities on dependable computing and other dependability issues in Japan.
Proceedings of the Building the Information Society, 2004

2003
Dependability Issue on Autonomic Computing Environment.
Proceedings of the 6th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2003), 2003

2002
Fault Tolerance in Autonomic Computing Environment.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

1999
Fault-tolerant neural networks with higher functionality.
Syst. Comput. Jpn., 1999

1996
Fault-Tolerant Design of Neural Networks for Solving Optimization Problems.
IEEE Trans. Computers, 1996

1995
Parameter estimation of hyper-geometric distribution software reliability growth model by genetic algorithms.
Proceedings of the Sixth International Symposium on Software Reliability Engineering, 1995

1993
Design of Neural Networks to Tolerate the Mixture of Two Types of Faults.
Proceedings of the Digest of Papers: FTCS-23, 1993

1992
Fault Tolerant Neural Networks in Optimization Problems.
Proceedings of the Digest of Papers: FTCS-22, 1992

1991
The Estimation of Parameters of the Hypergeometric Distribution and Its Application to the Software Reliability Growth Model.
IEEE Trans. Software Eng., 1991

Acceleration of timing verification method based on time petri nets.
Syst. Comput. Jpn., 1991

Parameter estimation of the hyper-geometric distribution model for real test/debug data.
Proceedings of the Second International Symposium on Software Reliability Engineering, 1991

Parameter Value Computation by Least Square Method and Evaluation of Software Availability and Reliability at Service-Operation by the Hyper-Geometric Distribution Software Reliability Growth Model (HGDM).
Proceedings of the 13th International Conference on Software Engineering, 1991

1990
The hyper-geometric distribution software reliability growth model (HGDM): precise formulation and applicability.
Proceedings of the Fourteenth Annual International Computer Software and Applications Conference, 1990

1989
Structural Approach to the Estimation of the Number of Residual Software Faults Based on the Hyper-Geometric Distribution.
IEEE Trans. Software Eng., 1989

A fast timing verification method based on the independence of units.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

Hyper-geometric distribution model to estimate the number of residual software faults.
Proceedings of the 13th Annual International Computer Software and Applications Conference, 1989

Models to estimate the number of faults still resident in the software after test/debug process.
Proceedings of the 13th Annual International Computer Software and Applications Conference, 1989

1988
A knowledge-based test generator for standard cell and iterative array logic circuits.
IEEE J. Solid State Circuits, April, 1988

1987
Test Generation for Large-Scale Combinational Circuits by Using Prolog.
Proceedings of the Logic Programming '87, 1987

1985
Interrupt handling in the loosely synchronized TMR system.
Syst. Comput. Jpn., 1985

1979
Universal Multicode STT State Assignments for Asynchronous Sequential Machines.
IEEE Trans. Computers, 1979

1978
On Universal Single Transition Time Asynchronous State Assignments.
IEEE Trans. Computers, 1978

1974
Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory.
IEEE Trans. Computers, 1974

A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits.
IEEE Trans. Computers, 1974

1971
Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code.
IEEE Trans. Computers, 1971

Failure-Tolerant Sequential Machines with Past Information.
IEEE Trans. Computers, 1971

1964
Decompositions of Logical Functions Using Majority Decision Elements.
IEEE Trans. Electron. Comput., 1964


  Loading...