Yoshihiro Shinozaki

According to our database, Yoshihiro Shinozaki authored at least 2 papers between 2005 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique.

Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara

IEEE J. Solid State Circuits, 2006

2005

A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor.

Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada

IEEE J. Solid State Circuits, 2005