Yoshiharu Watanabe

According to our database1, Yoshiharu Watanabe authored at least 2 papers between 2003 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2015
The world's 1st Complete-4K SoC solution with hybrid memory system.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2003
A Practical Approach for Bus Architecture Optimization at Transaction Level.
Proceedings of the 2003 Design, 2003


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