Yoshiharu Aimoto
According to our database1,
Yoshiharu Aimoto
authored at least 11 papers
between 1992 and 2011.
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Bibliography
2011
Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs.
IEEE J. Solid State Circuits, 2011
2006
IEEE J. Solid State Circuits, 2006
Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes.
IEEE J. Solid State Circuits, 2006
2001
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield.
IEEE J. Solid State Circuits, 2001
2000
IEEE J. Solid State Circuits, 2000
An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1998
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998
1995
Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications.
IEEE J. Solid State Circuits, June, 1995
1994
A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM.
IEEE J. Solid State Circuits, November, 1994
1993
IEEE J. Solid State Circuits, November, 1993
1992
IEEE J. Solid State Circuits, November, 1992