Yoshifumi Kawamoto

According to our database, Yoshifumi Kawamoto authored at least 7 papers between 1989 and 1992.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1992

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's.

Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh

IEEE J. Solid State Circuits, April, 1992

1991

A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture.

Katsutaka Kimura, Takeshi Sakata, Kiyoo Itoh, Toru Kaga, Takashi Nishida, Yoshifumi Kawamoto

IEEE J. Solid State Circuits, November, 1991

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's.

Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Yoshinobu Nakagome, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh

IEEE J. Solid State Circuits, November, 1991

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM.

Yoshinobu Nakagome, Kiyoo Itoh, Kan Takeuchi, Eiji Kume, Hitoshi Tanaka, Masanori Isoda, Tatsunori Musha, Toru Kaga, Teruaki Kisu, Takashi Nishida, Yoshifumi Kawamoto, Masakazu Aoki

IEEE J. Solid State Circuits, July, 1991

An experimental 1.5-V 64-Mb DRAM.

Yoshinobu Nakagome, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Yoshifumi Kawamoto, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, Kiyoo Itoh

IEEE J. Solid State Circuits, April, 1991

1989

A 1.5-V DRAM for battery-based applications.

Masakazu Aoki, Jun Etoh, Kiyoo Itoh, Shin Kimura, Yoshifumi Kawamoto

IEEE J. Solid State Circuits, October, 1989

New DRAM noise generation under half-V_cc precharge and its reduction using a transposed amplifier.

Masakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh

IEEE J. Solid State Circuits, August, 1989