Yoshiei Sato

According to our database, Yoshiei Sato authored at least 4 papers between 2007 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

Performance tuning and analysis of future vector processors based on the roofline model.

Yoshiei Sato, Ryu-ichi Nagaoka, Akihiro Musa, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi

Proceedings of the 10th workshop on MEmory performance, 2009

2008

A shared cache for a chip multi vector processor.

Akihiro Musa, Yoshiei Sato, Takashi Soga, Koki Okabe, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

Proceedings of the 9th workshop on MEmory performance, 2008

Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture.

Akihiro Musa, Yoshiei Sato, Takashi Soga, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

2007

An on-chip cache design for vector processors.

Akihiro Musa, Yoshiei Sato, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi

Proceedings of the 2007 workshop on MEmory performance, 2007