Yoshichika Fujioka
According to our database1,
Yoshichika Fujioka
authored at least 10 papers
between 1993 and 2014.
Collaborative distances:
Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2014
Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
2012
Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme.
Proceedings of the International SoC Design Conference, 2012
2009
Traveling-salesman game with multiple competitors/cooperators and simultaneous move search algorithm.
Proceedings of the 2009 International IEEE Consumer Electronics Society's Games Innovations Conference, 2009
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2000
Design of a WSI scale parallel processor for intelligent robot control based on a dynamic reconfiguration of multi-operand arithmetic units.
Syst. Comput. Jpn., 2000
1999
Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture.
Syst. Comput. Jpn., 1999
1996
Design of a Parallel Processor for Visual Feedback Control Based on the Reconfiguration of Word Length.
J. Robotics Mechatronics, 1996
1994
J. Robotics Mechatronics, 1994
1993
Proceedings of the 1993 IEEE International Conference on Robotics and Automation, 1993