Yoshiaki Kitaura

According to our database, Yoshiaki Kitaura authored at least 3 papers between 1990 and 1994.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

1994

A 20 GHz 8 bit multiplexer IC implemented with 0.5 μm WN_x/W-gate GaAs MESFET's.

Toshiki Seshita, Yoshiko Ikeda, Hirotsugu Wakimoto, Kenji Ishida, Toshiyuki Terada, Tokuhiko Matsunaga, Takashi Suzuki, Yoshiaki Kitaura, Naotaka Uchitomi

IEEE J. Solid State Circuits, December, 1994

1991

A 10-GHz 8-b multiplexer/demultiplexer chip set for the SONET STS-192 system.

Kenji Ishida, Hirotsugu Wakimoto, Kunio Yoshihara, Mitsuo Konno, Shoichi Shimizu, Yoshiaki Kitaura, Kenichi Tomita, Takashi Suzuki, Naotaka Uchitomi

IEEE J. Solid State Circuits, December, 1991

1990

An ECL-compatible GaAs SCFL design method.

Shoichi Shimizu, Kunio Yoshihara, Toshiyuki Terada, Kenji Ishida, Yoshiaki Kitaura, Chiaki Takubo

IEEE J. Solid State Circuits, April, 1990