Yorinobu Fujino
According to our database1,
Yorinobu Fujino
authored at least 2 papers
between 2024 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
2024
2025
0
1
2
1
1
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2025
A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm<sup>2</sup> Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture.
IEEE J. Solid State Circuits, January, 2025
2024
15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024