Yoontae Jung
Orcid: 0000-0003-0461-6729Affiliations:
- KAIST, Yuseong-gu, Daejeon, South Korea
According to our database1,
Yoontae Jung
authored at least 26 papers
between 2017 and 2024.
Collaborative distances:
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
On csauthors.net:
Bibliography
2024
A 187-dB FoM<sub>S</sub> Power-Efficient Second-Order Highpass ΔΣ Capacitance-to-Digital Converter.
IEEE J. Solid State Circuits, April, 2024
A Wide-Dynamic-Range, DC-Coupled, Time-Based Neural-Recording IC With Optimized CCO Frequency.
IEEE Access, 2024
A 5.7kfps Fast Neural Electrical Impedance Tomography IC Based on Incremental Zoom Structure with Baseline Cancellation for Peripheral Nerve Monitoring Systems.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
A Fully Dynamic 1<sup>st</sup>-Order Δ-ΔΣ Modulator with a 468mV<sub>pp</sub> Input Range for Electrical Impedance Tomography Systems.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
An Area-Efficient, DC-Coupled VCO-Based CT ΔΣM with Input-TR-DAC for Neural Recording.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A Reconfigurable Multimodal Sensor Interface IC Based on Direct-Conversion ΔΣ Modulator Structure.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A High-throughput Impedance Measurement IC Using Synchronous Cyclic Integration Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
A High-Efficiency Single-Mode Dual-Path Buck-Boost Converter With Reduced Inductor Current.
IEEE J. Solid State Circuits, March, 2023
A 2.5mW 12MHz-BW 69dB SNDR Passive Bandpass ΔΣ ADC with Highpass Noise-Shaping SAR Quantizers.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 187dB FoMS 46fJ/Conv 2<sup>nd</sup>-order Highpass Δ∑ Capacitance-to-Digital Converter.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Sub-aF Super-High-Resolution Capacitance-to-Digital Converter with a Bandpass ΔΣ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A 56fJ/Conversion-Step 178dB-FoMS Third-Order Hybrid CT-DT Δ∑ Capacitance-to-Digital Converter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
Dynamic-Range-Enhancement Techniques for Artifact-Tolerant Biopotential-Acquisition ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A PVT-Robust AFE-Embedded Error-Feedback Noise-Shaping SAR ADC With Chopper-Based Passive High-Pass IIR Filtering for Direct Neural Recording.
IEEE Trans. Biomed. Circuits Syst., 2022
A Wide-Dynamic-Range Neural-Recording IC With Automatic-Gain-Controlled AFE and CT Dynamic-Zoom ΔΣ ADC for Saturation-Free Closed-Loop Neural Interfaces.
IEEE J. Solid State Circuits, 2022
An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A Single-Mode Dual-Path Buck-Boost Converter with Reduced Inductor Current Across All Duty Cases Achieving 95.58% Efficiency at 1A in Boost Operation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 99.5dB-DR 5kHz-BW Closed-Loop Neural-Recording IC based on Continuous-Time Dynamic-Zoom ΔΣ ADC with Automatic AFE-Gain Control.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
Design of Reconfigurable Time-to-Digital Converter Based on Cascaded Time Interpolators for Electrical Impedance Spectroscopy.
Sensors, 2020
A 0.0046mm<sup>2</sup> 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A High DR, DC-Coupled, Time-Based Neural-Recording IC With Degeneration R-DAC for Bidirectional Neural Interface.
IEEE J. Solid State Circuits, 2019
2018
A 3.9μW, 81.3dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A neural recording amplifier based on adaptive SNR optimization technique for long-term implantation.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017