Yoonseo Cho
Orcid: 0000-0002-6832-7929
According to our database1,
Yoonseo Cho
authored at least 8 papers
between 2019 and 2025.
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Bibliography
2025
A 12.24-GHz MDLL With a 102-Multiplication Factor Using a Power-Gating-Based Ring Oscillator.
IEEE J. Solid State Circuits, February, 2025
2024
Unicorn: U-Net for Sea Ice Forecasting with Convolutional Neural Ordinary Differential Equations.
CoRR, 2024
2023
A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector.
IEEE J. Solid State Circuits, 2022
2021
An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2019
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators.
IEEE J. Solid State Circuits, 2019
A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019