Yoongu Kim
According to our database1,
Yoongu Kim
authored at least 28 papers
between 2004 and 2022.
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Bibliography
2022
Proceedings of the 31st USENIX Security Symposium, 2022
2018
Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems.
CoRR, 2018
CoRR, 2018
CoRR, 2018
2017
2016
Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses.
CoRR, 2016
2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
2014
The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
Memory Systems.
Proceedings of the Computing Handbook, 2014
2013
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
Linearly compressed pages: a low-complexity, low-latency main memory compression framework.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
MISE: Providing performance predictability and improving fairness in shared main memory systems.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
2012
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012
2011
2010
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010
2004
S-COI : The Secure Conflicts of Interest Model for Multilevel Secure Database Systems.
Proceedings of the Database Systems for Advances Applications, 2004