Yoon Seok Yang

Orcid: 0000-0001-6819-9974

According to our database1, Yoon Seok Yang authored at least 24 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Quantum-Secure Hybrid Blockchain System for DID-based Verifiable Random Function with NTRU Linkable Ring Signature.
CoRR, 2024

2023
Private and Secure Post-Quantum Verifiable Random Function with NIZK Proof and Ring-LWE Encryption in Blockchain.
CoRR, 2023

2021
Low-Power Cross-Layer Error Management Using MIMO-LDPC Iterative Decoding for Video Processing.
IEEE Access, 2021

2020
Recent Trend of Neuromorphic Computing Hardware: Intel's Neuromorphic System Perspective.
Proceedings of the International SoC Design Conference, 2020

An Energy-Efficient Imprecise Adder with a Lower-part Constant Approximation.
Proceedings of the International SoC Design Conference, 2020

2018
SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2015
Energy Harvesting from Upper-Limb Pulling Motions for Miniaturized Human-Powered Generators.
Sensors, 2015

2014
WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture.
ACM Trans. Design Autom. Electr. Syst., 2014

2013
Development and Functional Evaluation of an Upper Extremity Rehabilitation System Based on Inertial Sensors and Virtual Reality.
Int. J. Distributed Sens. Networks, 2013

2012
Unequal Error Protection Based on DVFS for JSCD in Low-Power Portable Multimedia Systems.
ACM Trans. Embed. Comput. Syst., 2012

Harvesting Energy from the Counterbalancing (Weaving) Movement in Bicycle Riding.
Sensors, 2012

Exploiting path diversity for low-latency and high-bandwidth with the dual-path NoC router.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Design space exploration for low-power channel decoder in embedded LDPC-H.264 joint decoding architecture.
Int. J. Inf. Technol. Commun. Convergence, 2011

Low-Power, Resilient Interconnection with Orthogonal Latin Squares.
IEEE Des. Test Comput., 2011

Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system.
Proceedings of the 48th Design Automation Conference, 2011

2010
Parallel processing for block ciphers on a fault tolerant networked processor array.
Int. J. High Perform. Syst. Archit., 2010

Low-power baseband processing for wireless multimedia systems using unequal error protection.
Proceedings of the 2010 Wireless Telecommunications Symposium, 2010

2009
Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip.
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

2008
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture.
Parallel Process. Lett., 2008

A Generic Network Interface Architecture for a Networked Processor Array (NePA).
Proceedings of the Architecture of Computing Systems, 2008

2006
A Portable Electronic Nose (E-Nose) System Based on PDA.
Proceedings of the Artificial Neural Networks, 2006

2004
Computer-aided diagnosis of solid breast nodules: use of an artificial neural network based on multiple sonographic features.
IEEE Trans. Medical Imaging, 2004

2001
Automatic identification of human helminth eggs on microscopic fecal specimens using digital image processing and an artificial neural network.
IEEE Trans. Biomed. Eng., 2001


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