Yongzhen Chen

Orcid: 0000-0002-1018-6289

According to our database¹, Yongzhen Chen authored at least 52 papers between 2013 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2024

A 0.5-V 0.02% THD Bulk-Driven OTA for Continuous-Time Applications in 180 nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024

A Foreground Wide-Band Receiver I/Q Mismatch Calibration Method in FDD Transceiver.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024

Design and Implementation of an EMI-Immune Daisy Chain Interface With a PID-Based CDR Algorithm for Battery Management System Communication.

[BibT_eX]

[DOI]

IEEE Access, 2024

A 40Gb/s Multi-band Wireline Receiver Analog Front-end for 50.4dB Channel Loss Compensation.

[BibT_eX]

[DOI]

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

2023

Research on monaural speech segregation based on feature selection.

[BibT_eX]

[DOI]

EURASIP J. Audio Speech Music. Process., December, 2023

A Wideband Receiver I/Q Mismatch Calibration Method in FDD Transceiver.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Foreground LSB-Based Capacitor Mismatch Calibration Method in An 18-bit SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 4.75-64 Gb/s PAM-4 Wireline Transmitter with 3-tap FFE in 28-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Nonlinear modeling of MIMO antenna array power amplifiers based on time-delay neural network.

[BibT_eX]

[DOI]

Yiwei Zhou

Weibo Li

Yongzhen Chen

Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Low-power Digital Automatic Gain Control Design in Wireless Communication Receivers.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

A low-power daisy-chain controller implemention in BMS based on power mode switching.

[BibT_eX]

[DOI]

Xinhao Xu

Yongzhen Chen

Jiangfeng Wu

Proceedings of the 15th IEEE International Conference on ASIC, 2023

Pipelined-SAR ADC Calibration Technique Based on Gain-Bit Weights.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

Complexity-Reduced Joint Calibration for Nonlinearity and I/Q Imbalance in Direct-Conversion Transmitters.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

A 32GS/s 7bit TI-SAR ADC in 28nm for 32Gb/s ADC-Based SerDes Receiver.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Feature Matching for Indoor-Oriented Visual Odometry.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Networking and Network Applications, 2022

A Current-Mode, 30 dB Range with 0.5 dB Step, 0.1 to 6 GHz Attenuator for Wideband Receiver.

[BibT_eX]

[DOI]

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 64Gb/s PAM-4 Digital Equalizer With Tap-Configurable FFE and Partially Unrolled DFE in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

0.7-6 GHz Programable Gain Push-Pull Driver PA Based on Dual-Loop Biases.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A 71dB DC Gain, 0.1% THD, 0.5-V Bulk-Driven Class-AB OTA Achieved by Novel CMFB Methods.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A 32Gb/s NRZ Wireline Transmitter with CMFB- Based CML Driver in 28nm CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A 2-GS/s 200-MHz BW Oversampling Continuous-Time Pipeline ADC with Adaptive Digital Filter in 28nm.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A 161mW 32Gb/s ADC-Based NRZ SerDes Receiver Front End in 28nm.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

An Input Buffer for 4 GS/s 14-b Time-Interleaved ADC.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

A 6-bit Active Phase Shifter with Quadrature Outputs.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Digital Calibration of Capacitor Mismatch and Gain Error in Pipelined SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Physical Coding Sublayer For 32Gbps SerDes Based On JESD204C.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

A High-Performance Mel-scale Frequency Cepstral Coefficients Digital Circuit Used on Keyword-Spotting Chip.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2019

A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic.

[BibT_eX]

[DOI]

Microelectron. J., 2019

A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps.

[BibT_eX]

[DOI]

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A Double-Latch Comparator for Multi-GS/s SAR ADCs in 28nm CMOS.

[BibT_eX]

[DOI]

Pingshun Ma

Yongzhen Chen

Jiangfeng Wu

Proceedings of the 13th IEEE International Conference on ASIC, 2019

An Area-Efficient Multi-Rate Digital Decimator.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

High Linear Ring Amplifier Design with Analysis on Settling Procedures.

[BibT_eX]

[DOI]

Yongzhen Chen

Jiangfeng Wu

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration.

[BibT_eX]

[DOI]

Yongzhen Chen

Fan Ye

Junyan Ren

Microelectron. J., 2018

A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches.

[BibT_eX]

[DOI]

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

An improved ring amplifier with process- and supply voltage-insensitive dead-zone.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A stacked-packaged 16-channel ADC for ultrasound application.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

An input buffer for 12bit 2GS/s ADC.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A proved dither-injection method for memory effect in double sampling pipelined ADC.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2015

A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2015, 2015

A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013

sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Yongzhen Chen

Timeline

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On csauthors.net:

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