Yongwoo Jo
Orcid: 0000-0003-0224-5979
According to our database1,
Yongwoo Jo
authored at least 18 papers
between 2015 and 2025.
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Bibliography
2025
A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces.
IEEE J. Solid State Circuits, February, 2025
2024
A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation.
IEEE J. Solid State Circuits, February, 2024
10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Field Experiments and Validation of Cooperative Driving for Conneced Automated Vehicle.
Proceedings of the 15th International Conference on Information and Communication Technology Convergence, 2024
2023
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier.
IEEE J. Solid State Circuits, December, 2023
A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25<sup>%</sup>-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop.
IEEE J. Solid State Circuits, 2022
2021
32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114.
IEEE J. Solid State Circuits, 2019
Real-time road surface marking detection from a bird's-eye view image using convolutional neural networks.
Proceedings of the Twelfth International Conference on Machine Vision, 2019
2018
An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique.
IEEE J. Solid State Circuits, 2018
153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Robust Ego-motion Estimation and Map Matching Technique for Autonomous Vehicle Localization with High Definition Digital Map.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2018
Vehicle re-identification for a parking lot toll system using convolutional neural networks.
Proceedings of the Eleventh International Conference on Machine Vision, 2018
Proceedings of the Eleventh International Conference on Machine Vision, 2018
2015
Precise Localization of an Autonomous Car Based on Probabilistic Noise Models of Road Surface Marker Features Using Multiple Cameras.
IEEE Trans. Intell. Transp. Syst., 2015