Yongsam Moon

According to our database, Yongsam Moon authored at least 14 papers between 1997 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2016

Signal detector for 6-Gbps 55-nm CMOS Serial ATA receiver.

Yongsam Moon

IEICE Electron. Express, 2016

2012

Divide-by-<i>N</i> and divide-by-<i>N</i>/<i>N</i>+1 prescalers based on a shift register and a multi-input NOR gate.

Seon-Woo Hwang, Yongsam Moon

IEICE Electron. Express, 2012

2010

A spread-spectrum clock generator for 6-Gbps Serial ATA transceiver.

Yongsam Moon

IEICE Electron. Express, 2010

2009

TX rise/fall time control for multi-rate serial link.

Yongsam Moon

IEICE Electron. Express, 2009

1.2V 1.6Gb/s 56nm 6F² 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture.

Yongsam Moon, Yong-Ho Cho, Hyun-Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

Presetting pulse-based flip-flop.

Chul Soo Kim, Joo-Seong Kim, Bai-Sun Kong, Yongsam Moon, Young-Hyun Jun

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2006

A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control.

Yongsam Moon, Gijung Ahn, Hoon Choi, Namhoon Kim, Daeyun Shim

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-μm CMOS.

Yongsam Moon, Sang-Hyun Lee, Daeyun Shim

IEEE J. Solid State Circuits, 2005

2004

A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link.

Yongsam Moon, Young-Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog-Kyoon Jeong

IEEE J. Solid State Circuits, 2004

2002

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit.

Sang-Hyun Lee, Moon-Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Bong-Joon Lee, Deog-Kyoon Jeong, Wonchan Kim, Young-June Park, Gijung Ahn

IEEE J. Solid State Circuits, 2002

2001

A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery.

Yongsam Moon, Deog-Kyoon Jeong, Gijung Ahn

IEEE J. Solid State Circuits, 2001

2000

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance.

Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim

IEEE J. Solid State Circuits, 2000

1999

A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells.

Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1997

A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL.

Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim

IEEE J. Solid State Circuits, 1997