Yongqiang Zhang
Orcid: 0000-0003-1403-9128Affiliations:
- Hefei University of Technology, School of Electronic Science and AppliedPhysics, China
According to our database1,
Yongqiang Zhang
authored at least 39 papers
between 2014 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Very Large Scale Integr. Syst., March, 2024
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024
Implementations of efficient non-blocking crossbar network with novel multiplexer design in quantum-dot cellular automata.
Nano Commun. Networks, 2024
A Low-Cost and Fault-Tolerant Stochastic Architecture for the Bernsen Algorithm Using Bitstream Correlation.
J. Circuits Syst. Comput., 2024
2023
Lightweight and flexible hardware implementation of authenticated encryption algorithm SIMON-Galois/Counter Mode.
Int. J. Circuit Theory Appl., December, 2023
An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023
Highly Accurate and Energy Efficient Binary-Stochastic Multipliers for Fault-Tolerant Applications.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
2022
IEEE Trans. Circuits Syst. Video Technol., 2022
Design and Implementation of SRAM for LUT and CLB Using Clocking Mechanism in Quantum-Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Weighted-Adder-Based Polynomial Computation Using Correlated Unipolar Stochastic Bitstreams.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A general and efficient clocking scheme for majority logic in quantum-dot cellular automata.
Microelectron. J., 2022
Int. J. Circuit Theory Appl., 2022
A stochastic computing architecture for local contrast and mean image thresholding algorithm.
Int. J. Circuit Theory Appl., 2022
High-accuracy mean circuits design by manipulating correlation for stochastic computing.
Int. J. Circuit Theory Appl., 2022
Highly accurate division and square root circuits by exploiting signal correlation in stochastic computing.
Int. J. Circuit Theory Appl., 2022
Int. J. Circuit Theory Appl., 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A reconfigurable and compact hardware architecture of CLEFIA block cipher with multi-configuration.
Microelectron. J., 2021
Microprocess. Microsystems, 2021
Design and implementation of programmable logic array using crossbar structure in quantum-dot cellular automata.
Int. J. Circuit Theory Appl., 2021
A high-resolution hybrid digital pulse width modulator with dual-edge-triggered flip-flops and hardware compensation.
Int. J. Circuit Theory Appl., 2021
Absolute Subtraction and Division Circuits Using Uncorrelated Random Bitstreams in Stochastic Computing.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
A Feedback Architecture of High Speed True Random Number Generator based on Ring Oscillator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A matrix representation method for decoders using majority gate characteristics in quantum-dot cellular automata.
J. Supercomput., 2020
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A robust wire crossing design for thermostability and fault tolerance in quantum-dot cellular automata.
Microprocess. Microsystems, 2020
J. Circuits Syst. Comput., 2020
CFE: a convenient, flexible, and efficient clocking scheme for quantum-dot cellular automata.
IET Circuits Devices Syst., 2020
High frequency and high efficiency DC-DC converter with sensorless adaptive-sizing technique.
IEICE Electron. Express, 2020
2019
Nano Commun. Networks, 2019
A Single-Input Multi-Output Piezoelectric Energy Harvesting System Combining with P-SSHI and Cold Startup Circuit.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
J. Electron. Test., 2018
2017
Microprocess. Microsystems, 2017
2016
Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates.
Int. J. Circuit Theory Appl., 2016
2014
Design and Implementation of Encoding and Check Code Circuit with Hamming Code on QCA.
Int. J. Unconv. Comput., 2014