Yongliang Zhou

According to our database, Yongliang Zhou authored at least 29 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense.

Yongliang Zhou, Xiao Lin, Zixuan Zhou, Yingxue Sun, Yiming Wei, Zhen Yang, Chengxing Dai, JingXue Zhong, Xiulong Wu, Chunyu Peng

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024

Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design.

Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., May, 2024

Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies.

Licai Hao, Xinyi Zhang, Chenghu Dai, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., April, 2024

A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices.

Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices.

Yongliang Zhou, Yiming Wei, Tianzhu Xiong, Zixuan Zhou, Zhen Yang, Xiao Lin, Wei Hu, Xiulong Wu, Chunyu Peng

Microelectron. J., 2024

Configurable in-memory computing architecture based on dual-port SRAM.

Yue Zhao, Yunlong Liu, Jian Zheng, Zhongzhen Tong, Xin Wang, Runru Yu, Xiulong Wu, Yongliang Zhou, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Zhiting Lin

Microelectron. J., 2024

Ultra8T: A sub-threshold 8T SRAM with leakage detection.

Shan Shen, Hao Xu, Yongliang Zhou, Ming Ling, Wenjian Yu

Integr., 2024

A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM.

Yongliang Zhou, Zhen Yang, Yiming Wei, Xiao Lin, Saiai Wu, Wenjuan Lu, Chunyu Peng, Xin Li, Xiulong Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

A Single-Ended Offset-Canceling Sense Amplifier Enabling Wide-Voltage Operations.

Shan Shen, Hao Xu, Yongliang Zhou, Wenjian Yu

IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks.

Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren, Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.

An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.

Hao Cai, Zhong-Jian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu, Xin Si, Zhen Wang, Jun Yang, Weiwei Shan

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

Writing-only in-MRAM computing paradigm for ultra-low power applications.

Bo Liu, Mingyue Liu, Yongliang Zhou, Xiaofeng Hong, Hao Cai, Lirida Alves de Barros Naviner

Microprocess. Microsystems, April, 2022

SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation.

Bo Wang, Chen Xue, Han Liu, Xiang Li, Anran Yin, Zhongyuan Feng, Yuyao Kong, Tianzhu Xiong, Haiming Hsu, Yongliang Zhou, An Guo, Yufei Wang, Jun Yang, Xin Si

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations.

An Guo, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Chen Xue, Yufei Wang, Xin Si, Jun Yang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN Accelerators.

Yongliang Zhou, Zuo Cheng, Han Liu, Tianzhu Xiong, Bo Wang

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration.

Hao Cai, Juntong Chen, Yongliang Zhou, Weisheng Zhao

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A survey of in-spin transfer torque MRAM computing.

Hao Cai, Bo Liu, Juntong Chen, Lirida A. B. Naviner, Yongliang Zhou, Zhen Wang, Jun Yang

Sci. China Inf. Sci., 2021

Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices.

Yufei Wang, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xin Si

Proceedings of the International Conference on UK-China Emerging Technologies, 2021

Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices.

Tianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang

Proceedings of the 18th International SoC Design Conference, 2021

Challenge and Trend of SRAM Based Computation-in-Memory Circuits for AI Edge Devices.

Xin Si, Yongliang Zhou, Jun Yang, Meng-Fan Chang

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM.

Yongliang Zhou, Hao Cai, Lei Xie, Menglin Han, Mingyue Liu, Shi Xu, Bo Liu, Weisheng Zhao, Jun Yang

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing.

Yongliang Zhou, Hao Cai, Bo Liu, Weisheng Zhao, Jun Yang

IEEE Trans. Circuits Syst., 2020

Magnetic Tunnel Junction Applications.

Nilson Maciel, Elaine Crespo Marques, Lirida A. B. Naviner, Yongliang Zhou, Hao Cai

Sensors, 2020

Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing.

Hao Cai, Honglan Jiang, Yongliang Zhou, Menglin Han, Bo Liu

CCF Trans. High Perform. Comput., 2020

2019

A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement.

Yongliang Zhou, Menglin Han, Mingyue Liu, Hao Cai, Bo Liu, Jun Yang

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

2016

Robust activating timing for SRAM SA with replica cell voltage boosted circuit.

Zhengping Li, Mingming Xie, Xincun Ji, Yongliang Zhou

IEICE Electron. Express, 2016

2011

Rank-two residue iteration method for nonnegative matrix factorization.

Hongwei Liu, Yongliang Zhou

Neurocomputing, 2011

2010

Analysis of how to use the GEB developing.

Na Wei, Yongliang Zhou

Proceedings of the International Conference on E-Business and E-Government, 2010