Yongkee Kwon

Orcid: 0009-0001-9511-4734

According to our database1, Yongkee Kwon authored at least 20 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
Cost-Effective LLM Accelerator Using Processing in Memory Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

IANUS: Integrated Accelerator based on NPU-PIM Unified Memory System.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application.
IEEE J. Solid State Circuits, 2023

Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics.
CoRR, 2023


2022
A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Holistic approaches to memory solutions for the Autonomous Driving Era.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022


2020
Near Data Acceleration with Concurrent Host Access.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019
CHoNDA: Near Data Acceleration with Concurrent Host Access.
CoRR, 2019

Mini-batch Serialization: CNN Training with Inter-layer Data Reuse.
Proceedings of the Second Conference on Machine Learning and Systems, SysML 2019, 2019

2018
ERUCA: Efficient DRAM Resource Utilization and Resource Conflict Avoidance for Memory System Parallelism.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Rank-Level Parallelism in DRAM.
IEEE Trans. Computers, 2017

Refresh-Aware Write Recovery Memory Controller.
IEEE Trans. Computers, 2017

A Distributed Multi-GPU System for Fast Graph Processing.
Proc. VLDB Endow., 2017

2016
DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing.
IEEE Trans. Computers, 2016

Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation.
IEEE Trans. Computers, 2016

Adaptive and flexible key-value stores through soft data partitioning.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Accelerating Linked-list Traversal Through Near-Data Processing.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Multiple clone row DRAM: a low latency and area optimized DRAM.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015


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