Yong Zheng

Orcid: 0000-0001-8569-2680

Affiliations:

Chinese Academy of Sciences, Aerospace Information Research Institute, Beijing, China
Chinese Academy of Sciences, Institute of Electronics, Beijing, China

According to our database¹, Yong Zheng authored at least 7 papers between 2019 and 2022.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Bibliography

2022

Optimizing Off-Chip Memory Access for Deep Neural Network Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

mTREE: A Customized Multicast-Enabled Tree-Based Network on Chip for AI Chips.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2022

2021

A Resource and Performance Optimization Reduction Circuit on FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2021

A Novel Reduction Circuit Based on Binary Tree Path Partition on FPGAs.

[BibT_eX]

[DOI]

Algorithms, 2021

2019

A High Energy-Efficiency FPGA-Based LSTM Accelerator Architecture Design by Structured Pruning and Normalized Linear Quantization.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

A Resource Consumption and Performance Overhead Optimized Reduction Circuit on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

Exploring Resource-Efficient Acceleration Algorithm for Transposed Convolution of GANs on FPGA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

Yong Zheng

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