Yong Liu

According to our database, Yong Liu authored at least 20 papers between 2002 and 2016.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2016

A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.

Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman

IEEE J. Solid State Circuits, 2016

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.

Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman

IEEE J. Solid State Circuits, 2015

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.

Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.

Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, Leland Chang, José A. Tierno, Daniel J. Friedman

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman

IEEE J. Solid State Circuits, 2012

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS.

Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman

IEEE J. Solid State Circuits, 2012

A compact low-power 3D I/O in 45nm CMOS.

Yong Liu, Wing K. Luk, Daniel J. Friedman

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS.

Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Solid-state and biological systems interface.

Nan Sun, Yong Liu, Ling Qin, Guangyu Xu, Donhee Ham

Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.

Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, José A. Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2009

CMOS RF Biosensor Utilizing Nuclear Magnetic Resonance.

Nan Sun, Yong Liu, Hakho Lee, Ralph Weissleder, Donhee Ham

IEEE J. Solid State Circuits, 2009

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS.

Byungsub Kim, Yong Liu, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman

IEEE J. Solid State Circuits, 2009

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS.

Yong Liu, Byungsub Kim, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

Fast-Lock Hybrid PLL Combining Fractional-N and Integer-N Modes of Differing Bandwidths.

Kyoungho Woo, Yong Liu, Eunsoo Nam, Donhee Ham

IEEE J. Solid State Circuits, 2008

CMOS Mini Nuclear Magnetic Resonance System and its Application for Biomolecular Sensing.

Yong Liu, Nan Sun, Hakho Lee, Ralph Weissleder, Donhee Ham

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs.

Yong Liu, Woogeun Rhee, Daniel J. Friedman, Donhee Ham

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

IC/microfluidic hybrid system for magnetic manipulation of biological cells.

Hakho Lee, Yong Liu, Robert M. Westervelt, Donhee Ham

IEEE J. Solid State Circuits, 2006

2002

A Flexible Embedded SRAM Compiler.

Yong Liu, Zhiqiang Gao, Xiangqing He

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002