Yong Li

Affiliations:

University of Pittsburgh, Department of ECE, PA, USA

According to our database¹, Yong Li authored at least 16 papers between 2010 and 2015.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2015

Read Performance: The Newest Barrier in Scaled STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Improving efficiency of wireless sensor networks through lightweight in-memory compression.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Space Oblivious Compression: Power Reduction for Non-Volatile Main Memories.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Multilane Racetrack caches: Improving efficiency through compression and independent shifting.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

A Practical Data Classification Framework for Scalable and High Performance Chip-Multiprocessors.

[BibT_eX]

[DOI]

Yong Li

Rami G. Melhem

Alex K. Jones

IEEE Trans. Computers, 2014

Prefetching techniques for STT-RAM based last-level cache in CMP systems.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

C1C: A configurable, compiler-guided STT-RAM L1 cache.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

PS-TLB: Leveraging page classification information for fast, scalable and efficient translation for future CMPs.

[BibT_eX]

[DOI]

Yong Li

Rami G. Melhem

Alex K. Jones

ACM Trans. Archit. Code Optim., 2013

2012

Compiler-Assisted Data Distribution and Network Configuration for Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2012

Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2012

Cross-Layer Techniques for Optimizing Systems Utilizing Memories with Asymmetric Access Characteristics.

[BibT_eX]

[DOI]

Yong Li

Alex K. Jones

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A software approach for combating asymmetries of non-volatile memories.

[BibT_eX]

[DOI]

Yong Li

Yiran Chen

Alex K. Jones

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Asymmetry of MTJ switching and its implication to STT-RAM designs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Practically private: enabling high performance CMPs through compiler-assisted data classification.

[BibT_eX]

[DOI]

Yong Li

Rami G. Melhem

Alex K. Jones

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2010

Compiler-assisted data distribution for chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

Yong Li

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