Yong Hei
Orcid: 0000-0002-8025-2739
According to our database1,
Yong Hei
authored at least 27 papers
between 2010 and 2020.
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Bibliography
2020
IEEE Trans. Circuits Syst., 2020
Erratum: A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance [IEICE Electronics Express Vol. 16 (2019) No. 14 pp. 20190342].
IEICE Electron. Express, 2020
Erratum: Snake: An asynchronous pipeline for ultra-low-power applications [IEICE Electronics Express Vol. 16 (2019) No. 12 pp. 20190293].
IEICE Electron. Express, 2020
2019
A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance.
IEICE Electron. Express, 2019
IEICE Electron. Express, 2019
IEICE Electron. Express, 2019
IEICE Electron. Express, 2019
2018
A practical, low-overhead, one-cycle correction design method for variation-tolerant digital circuits.
IEICE Electron. Express, 2018
IEICE Electron. Express, 2018
A low power and glitch-free circular rotation phase modulator for outphasing transmitter.
IEICE Electron. Express, 2018
Proceedings of the 47th International Conference on Parallel Processing, 2018
2017
A Low-Voltage SRAM Sense Amplifier With Offset Cancelling Using Digitized Multiple Body Biasing.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
An improved phase digitization mechanism for fast-locking low-power all-digital PLLs.
IEICE Electron. Express, 2017
Erratum: A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes [IEICE Electronics Express Vol. 14 (2017) No. 15 pp. 20170660].
IEICE Electron. Express, 2017
A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes.
IEICE Electron. Express, 2017
IEICE Electron. Express, 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
A Low Power, High Performance Analog Front-End Circuit for 1 V Digital Hearing Aid SoC.
Circuits Syst. Signal Process., 2015
A low voltage SRAM sense amplifier with offset cancelling using digitized multiple body biasing.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
J. Commun., 2010
Proceedings of the Fifth International Conference on Frontier of Computer Science and Technology, 2010