Yong Chen
Orcid: 0000-0002-2794-1324Affiliations:
- University of Macau, State Key Laboratory of Analog and Mixed-Signal, Macau
- Nanyang Technological University, Singapore (2013 - 2016)
- Tsinghua University, Institute of Microelectronics, Beijing, China (2010 - 2013)
- Chinese Academy of Sciences, Institute of Microelectronics, China (PhD 2010)
According to our database1,
Yong Chen
authored at least 110 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on orcid.org
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on amsv.umac.mo
On csauthors.net:
Bibliography
2024
A 28-nm Dual-Mode Explicit Class-F₂₃ VCO With Low-Loss CM Return Path Achieving 70-400-kHz 1/f³ PN Corner Over 4.9-7.3-GHz TR.
IEEE Trans. Very Large Scale Integr. Syst., September, 2024
Extended Power Dynamic Range and Enhanced Power Conversion Efficiency of a Switched-Capacitor DC-DC Converter: A Tutorial.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
7.4 A 0.027mm<sup>2</sup> 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 0.144 mm<sup>2</sup>12.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A Fully Integrated CMOS Tri-Band Ambient RF Energy Harvesting System for IoT Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
P<sup>3</sup> ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A 28-nm 368-fJ/Cycle, 0.43%/V Supply-Sensitivity, FLL-Based RC Oscillator Featuring Positive-TC-Only Resistors and ΔΣM-Based Trimming.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023
A 0.004-mm<sup>2</sup> 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS.
IEEE J. Solid State Circuits, November, 2023
A Reconfigurable CMOS Stack Rectifier With 22.8-dB Dynamic Range Achieving 47.91% Peak PCE for IoT/WSN Application.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
A High-PCE Range-Extension CMOS Rectifier Employing Advanced Topology Amalgamation Technique for Ambient RF Energy Harvesting.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
A 0.0043-mm<sup>2</sup> 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023
A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation.
Int. J. Circuit Theory Appl., May, 2023
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
A 3.78-GHz Type-I Sampling PLL With a Fully Passive K<sub>PD</sub>-Doubled Primary-Secondary S-PD Measuring 39.6-fs<sub>RMS</sub> Jitter, -260.2-dB FOM, and -70.96-dBc Reference Spur.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor.
Int. J. Circuit Theory Appl., April, 2023
IEEE Trans. Very Large Scale Integr. Syst., February, 2023
A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fs<sub>RMS</sub>Jitter, -258.7-dB FOM, and -75.17-dBc Reference Spur.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023
A Subthreshold Operation Series-Parallel Charge Pump Incorporating Dynamic Source-Fed Oscillator for Wide-Input-Voltage Energy Harvesting Application.
IEEE Access, 2023
A Fully-Integrated CMOS Dual-Band RF Energy Harvesting Front-End Employing Adaptive Frequency Selection.
IEEE Access, 2023
High-Performance Multiband Ambient RF Energy Harvesting Front-End System for Sustainable IoT Applications - A Review.
IEEE Access, 2023
Design Trends and Perspectives of Digital Low Dropout Voltage Regulators for Low Voltage Mobile Applications: A Review.
IEEE Access, 2023
A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz $\text{FoM}_{\mathrm{T}}$.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2<sup>nd</sup>-Harmonic Output.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A 0.0035-mm<sup>2</sup> 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 72-Channel Resistive-and-Capacitive Sensor Interface Achieving 0.74 μ W/ Channel and 0.038 mm<sup>2</sup>/ Channel by Noise-Orthogonalizing and Pad-Sharing Techniques.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A -20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm<sup>2</sup> FoM for RF-Based Hybrid Energy Harvesting.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A 6.5-mm<sup>2</sup> 10.5-to-15.5-GHz Differential GaN PA With Coupled-Line-Based Matching Networks Achieving 10-W Peak P<sub>sat</sub> and 42% PAE.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 0.1-V V<sub>IN</sub> Subthreshold 3-Stage Dual-Branch Charge Pump With 43.4% Peak Power Conversion Efficiency Using Advanced Dynamic Gate-Bias.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Square-Wave Stimulated DNA Analyzer Chip Featuring 120μW Power Consumption and Simultaneous Dual-Frequency Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Millimeter-Wave CMOS VCO Featuring a Mode-Ambiguity-Aware Multi-Resonant-RLCM Tank.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Correction: Zhang et al. A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components. Sensors 2022, 22, 5852.
Sensors, 2022
A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components.
Sensors, 2022
A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection.
Sensors, 2022
Sensors, 2022
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 0.0285-mm<sup>2</sup> 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration.
IEEE J. Solid State Circuits, 2022
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR.
IEEE J. Solid State Circuits, 2022
A 23- to 28-GHz 5-bit switch-type phase shifter with 1-bit calibration based on optimized ABCD matrix design methods for 5G MIMO system in 0.15-μm GaAs.
Int. J. Circuit Theory Appl., 2022
A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology.
Int. J. Circuit Theory Appl., 2022
Low Voltage Switched-Capacitive-Based Reconfigurable Charge Pumps for Energy Harvesting Systems: An Overview.
IEEE Access, 2022
IEEE Access, 2022
A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022
A Flexible-Window Filtering Technique for Interference Suppression in SpO2 Monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A 0.01mm<sup>2</sup>, 0.4V-VDD, 4.5nW-Power DC-Coupled Digital Acquisition Front-End Based on Time-Multiplexed Digital Differential Amplification.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022
A Battery-Less Crystal-Less 49.8µW Neural-Recording Chip Featuring Two-Tone RF Power Harvesting.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A 0.006-mm<sup>2</sup>6-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A 0.004-mm<sup>2</sup> O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-Distorter (DAAPD) Reconfigurable Linearization Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 3.36-GHz Locking-Tuned Type-I Sampling PLL With -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 0.003-mm<sup>2</sup> 440fs<sub>RMS</sub>-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
An accelerated architecture of change-point detection for FMCW radar mutual interference based on FPGA.
Int. J. Circuit Theory Appl., 2021
Int. J. Circuit Theory Appl., 2021
A 120-150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm P<sub>sat</sub> for Sub-THz Imaging System.
IEEE Access, 2021
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS.
IEEE Access, 2021
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique.
IEEE Access, 2021
A 5.0-to-6.36GHz Wideband-Harmonic-Shaping VCO Achieving 196.9dBc/Hz Peak FoM and 90-to-180kHz 1/f<sup>3</sup> PN Corner Without Harmonic Tuning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression and Circulation, Achieving -151-dBc/Hz Phase Noise at 10-MHz Offset.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A 4×25Gb/s De-Serializer with Baud-Rate Sampling CDR and Standing-Wave Clock Distribution for NIC Optical Interconnects.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021
A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio.
Proceedings of the 47th ESSCIRC 2021, 2021
A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021
2020
A 3.3-mW 25.2-to-29.4-GHz Current-Reuse VCO Using a Single-Turn Multi-Tap Inductor and Differential-Only Switched-Capacitor Arrays With a 187.6-dBc/Hz FOM.
IEEE Trans. Circuits Syst., 2020
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector.
IEEE Access, 2020
A 0.024-mm<sup>2</sup> 45.4-GHz-Bandwidth Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
A 0.0285mm<sup>2</sup> 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A 0.0018-mm<sup>2</sup> 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-g<sub>m</sub> Cell.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 0.044-mm<sup>2</sup> 0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 0.0071-mm<sup>2</sup> 10.8ps<sub>pp</sub>-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6dBc/Hz FoM and 130kHz 1/f3 PN Corner.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 0.003-mm<sup>2</sup> 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
A 0.013-mm<sup>2</sup> 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2018
A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2015
A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable for 10-Gb/s I/O Links.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2013
A Fifth-Order 20-MHz Transistorized-LC-Ladder LPF With 58.2-dB SFDR, 68-µW/Pole/MHz Efficiency, and 0.13-mm<sup>2</sup> Die Size in 90-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A Single-Branch Third-Order Pole-Zero Low-Pass Filter With 0.014-mm<sup>2</sup> Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth-Power Scalability.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010