Yoichi Yuyama
According to our database1,
Yoichi Yuyama
authored at least 7 papers
between 2004 and 2011.
Collaborative distances:
Collaborative distances:
Timeline
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2005
2006
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2011
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2011
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.
IEICE Trans. Electron., 2011
Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2006
IEICE Trans. Electron., 2006
2005
A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
RTL/ISS co-modeling methodology for embedded processor using SystemC.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An SoC architecture and its design methodology using unifunctional heterogeneous processor array.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004