Yoichi Yoshida

According to our database1, Yoichi Yoshida authored at least 13 papers between 2008 and 2012.

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Bibliography

2012
6 W/25 mm<sup>2</sup> Wireless Power Transmission for Non-contact Wafer-Level Testing.
IEICE Trans. Electron., 2012

2011
6W/25mm<sup>2</sup> inductive power transfer for non-contact wafer-level testing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 2.7Gb/s/mm<sup>2</sup> 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing.
IEEE J. Solid State Circuits, 2010

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.
IEEE J. Solid State Circuits, 2010

Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link.
IEICE Trans. Electron., 2010

A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array.
IEEE J. Solid State Circuits, 2008


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