Yoichi Kawano
According to our database1,
Yoichi Kawano
authored at least 15 papers
between 2003 and 2024.
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Bibliography
2024
A neural network-based DPD coefficient determination for PA linearization in 5G and beyond-5G mmWave systems.
IEICE Electron. Express, 2024
2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
Beyond 110 GHz InP-HEMT Based Mixer Module Using Flip-Chip Assembly for Precise Spectrum Analysis.
IEICE Trans. Electron., 2015
2014
A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE.
IEEE J. Solid State Circuits, 2014
3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2012
A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
A 50-Gbit/s 450-mW Full-Rate 4: 1 Multiplexer With Multiphase Clock Architecture in 0.13-µm InP HEMT Technology.
IEEE J. Solid State Circuits, 2007
2003
Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003