Yogesh Singh Chauhan

Adv. Intell. Syst., August, 2024

GaN-based wide-band high-efficiency power amplifier with multi harmonic resonance.

[BibT_eX]

[DOI]

Microelectron. J., 2024

Design and experimental validation of class-F-1 GaN power amplifier using a compact harmonic control unit.

[BibT_eX]

[DOI]

Microelectron. J., 2024

Energy-Efficient Cryogenic Ternary Content Addressable Memory using Ferroelectric SQUID.

[BibT_eX]

[DOI]

Shamiul Alam

Simon Thomann

CoRR, 2024

Optimizing Low Noise Amplifiers: A Two-Stage Approach for Improved Noise Figure and Stability.

[BibT_eX]

[DOI]

IEEE Access, 2024

Enhancing the Capabilities of Quantum Transport Simulations Utilizing Machine Learning Strategies.

[BibT_eX]

[DOI]

Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Technology Mapping for Cryogenic CMOS Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction.

[BibT_eX]

[DOI]

Girish Pahwa

Proceedings of the IEEE International Reliability Physics Symposium, 2024

On the Severity of Self-Heating in FDSOI at Cryogenic Temperatures: In-depth Analysis from Transistors to Full Processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023

SCANet: Securing the Weights With Superparamagnetic-MTJ Crossbar Array Networks.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., September, 2023

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

A Computationally Efficient Compact Model for Ferroelectric Switching With Asymmetric Nonperiodic Input Signals.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

An Ultra-Low Noise Figure and Multi-Band Re-Configurable Low Noise Amplifier.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023

FerroCoin: Ferroelectric Tunnel Junction-Based True Random Number Generator.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2023

Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

Robust Compact Model of High-Voltage MOSFET's Drift Region.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2023

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.

[BibT_eX]

[DOI]

Muhammad Shaffatul Islam

Vijaykrishnan Narayanan

Kai Ni

CoRR, 2023

Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs.

[BibT_eX]

[DOI]

CoRR, 2023

Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration.

[BibT_eX]

[DOI]

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Invited Paper: Ultra-Efficient Edge AI Using FeFET-based Monolithic 3D Integration.

[BibT_eX]

[DOI]

Shubham Kumar

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing.

[BibT_eX]

[DOI]

Proceedings of the Device Research Conference, 2023

Design Automation for Cryogenic CMOS Circuits.

[BibT_eX]

[DOI]

Victor M. van Santen

Marcel Walter

Florian Klemme

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Ferroelectric FET-Based Implementation of FitzHugh-Nagumo Neuron Model.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Analytical approximation of surface potential and analysis of C-V characteristics of bulk MOSFETs at cryogenic temperatures.

[BibT_eX]

[DOI]

Wajid Manzoor

Aloke K. Dutta

Microelectron. J., 2022

Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

Kai Ni

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Cross-layer FeFET Reliability Modeling for Robust Hyperdimensional Computing.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

A GaN Based Reverse Recovery Time Limiter Circuit Integrated with a Low Noise Amplifier.

[BibT_eX]

[DOI]

Neha Bajpai

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

Novel FDSOI-based Dynamic XNOR Logic for Ultra-Dense Highly-Efficient Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Self-Heating characterization and modeling of 5nm technology node FinFETs.

[BibT_eX]

[DOI]

Eduardo Antonio Cesar da Costa

Proceedings of the Device Research Conference, 2022

Impact of Corner Rounding on Quantum Confinement in GAA Nanosheet FETs for Advanced Technology Nodes.

[BibT_eX]

[DOI]

Proceedings of the Device Research Conference, 2022

A width-scalable SPICE compact model for GaN HEMTs including self-heating effect.

[BibT_eX]

[DOI]

Proceedings of the Device Research Conference, 2022

2021

PROTON: Post-Synthesis Ferroelectric Thickness Optimization for NCFET Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

On the Resiliency of NCFET Circuits Against Voltage Over-Scaling.

[BibT_eX]

[DOI]

Sergio Bampi

Jörg Henkel

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Improved modeling of flicker noise including velocity saturation effect in FinFETs and experimental validation.

[BibT_eX]

[DOI]

Ravi Goel

Weike Wang

Microelectron. J., 2021

Study of multi-domain switching dynamics in negative capacitance FET using SPICE model.

[BibT_eX]

[DOI]

Amol D. Gaidhane

Amit Verma

Microelectron. J., 2021

Impact of NCFET on Neural Network Accelerators.

[BibT_eX]

[DOI]

Georgios Zervakis

Iraklis Anagnostopoulos

IEEE Access, 2021

A Low Noise Power Amplifier MMIC to Mitigate Co-Site Interference in 5G Front End Modules.

[BibT_eX]

[DOI]

IEEE Access, 2021

Transistor Self-Heating: The Rising Challenge for Semiconductor Testing.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

2020

Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Associative processing using negative capacitance FDSOI transistor for pattern recognition.

[BibT_eX]

[DOI]

Dinesh Rajasekharan

Pragya Kushwaha

Microelectron. J., 2020

Power Side-Channel Attacks in Negative Capacitance Transistor.

[BibT_eX]

[DOI]

IEEE Micro, 2020

Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET).

[BibT_eX]

[DOI]

CoRR, 2020

Impact of Radiation on Negative Capacitance FinFET.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Cell Library Characterization using Machine Learning for Design Technology Co-Optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

NCFET to Rescue Technology Scaling: Opportunities and Challenges.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications.

[BibT_eX]

[DOI]

Dinesh Rajasekharan

Amit Ranjan Trivedi

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

NCFET-Aware Voltage Scaling.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance.

[BibT_eX]

[DOI]

IEEE Access, 2018

Non-Linear RF Modeling of GaN HEMTs with Industry Standard ASM GaN Model (Invited).

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018

2017

Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2016

Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG.

[BibT_eX]

[DOI]

Microelectron. J., 2016

Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor.

[BibT_eX]

[DOI]

Chandan Yadav

Amit Agarwal

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015

Modeling STI Edge Parasitic Current for Accurate Circuit Simulations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

BSIM-CMG: Standard FinFET compact model for advanced circuit design.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2015, 2015

2014

BSIM6 - Benchmarking the Next-Generation MOSFET Model for RF Applications.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013

BSIM - SPICE Models Enable FinFET and UTB IC Designs.

[BibT_eX]

[DOI]

Navid Paydavosi

IEEE Access, 2013

BSIM compact MOSFET models for SPICE simulation.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

2012

BSIM - Industry standard compact MOSFET models.

[BibT_eX]

[DOI]

Proceedings of the 38th European Solid-State Circuit conference, 2012

Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology.

[BibT_eX]

[DOI]

Maria-Anna Chalkiadaki

Anurag Mangla

Christian C. Enz

Mohammed Ahosan Ul Karim

Ali M. Niknejad

Chenming Hu

Proceedings of the 38th European Solid-State Circuit conference, 2012

2010

RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2008

Compact Modeling of Suspended Gate FET.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling.

[BibT_eX]

[DOI]

François Krummenacher

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Suspended-gate FET as a sleep transistor for ultra-low stand-by power applications.

[BibT_eX]

[DOI]

Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

2006

A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor.

[BibT_eX]

[DOI]