Yogesh S. Mahajan

According to our database1, Yogesh S. Mahajan authored at least 8 papers between 2004 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

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Bibliography

2011
Specification and encoding of transaction interaction properties.
Formal Methods Syst. Des., 2011

2010
Utility of transaction-level hardware models in refinement checking.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2009
Supporting RTL flow compatibility in a microarchitecture-level design framework.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2007
Verification Driven Formal Architecture and Microarchitecture Modeling.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Automating Hazard Checking in Transaction-Level Microarchitecture Models.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

2005
Verification Languages.
Proceedings of the Embedded Systems Handbook., 2005

Verification Languages.
Proceedings of the Industrial Information Technology Handbook, 2005

2004
Zchaff2004: An Efficient SAT Solver.
Proceedings of the Theory and Applications of Satisfiability Testing, 2004


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