Yo-Hao Tu

According to our database, Yo-Hao Tu authored at least 13 papers between 2010 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications.

Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng

IEEE Trans. Very Large Scale Integr. Syst., 2021

2019

A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET.

Jieqiong Du, Chien-Heng Wong, Yo-Hao Tu, Wei-Han Cho, Yilei Li, Yuan Du, Po-Tsang Huang, Sheau Jiung Lee, Mau-Chung Frank Chang

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

2018

A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection.

Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, Jen-Chieh Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Low supply voltage and multiphase all-digital crystal-less clock generator.

Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Chi-Yang Chang

IET Circuits Devices Syst., 2018

A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application.

Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering.

Yo-Hao Tu, Kai-Wen Yao, Minghao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, Jia-Shiang Fu

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016

Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture.

Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng

IEICE Trans. Electron., 2016

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC.

Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu

IEICE Electron. Express, 2016

A chaotically injected timing technique for ring-based oscillators.

Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

A Synchronous Mirror Delay with Duty-Cycle Tunable Technology.

Yo-Hao Tu, Kuo-Hsing Cheng, Yian-An Lin, Hong-Yi Huang

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

A low supply voltage synchronous mirror delay with quadrature phase output.

Yo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, Hong-Yi Huang

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013

A low jitter delay-locked-loop applied for DDR4.

Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, Hong-Yi Huang

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2010

A 3 GHz DLL-based clock generator with stuck locking protection.

Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, Kuo-Hsing Cheng

Proceedings of the 17th IEEE International Conference on Electronics, 2010