Yize Wang

According to our database, Yize Wang authored at least 12 papers between 2016 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

A Scalable Model for Snapback Characteristics of Circuit-Level ESD Simulation.

Zilong Shen, Yize Wang, Yunhao Li, Xing Zhang, Yuan Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Hybrid Model Based on Superpixel Entropy Discrimination for PolSAR Image Classification.

Jili Sun, Lingdong Geng, Yize Wang

Remote. Sens., 2022

QuickPose: Real-time Multi-view Multi-person Pose Estimation in Crowded Scenes.

Zhize Zhou, Qing Shuai, Yize Wang, Qi Fang, Xiaopeng Ji, Fashuai Li, Hujun Bao, Xiaowei Zhou

Proceedings of the SIGGRAPH '22: Special Interest Group on Computer Graphics and Interactive Techniques Conference, Vancouver, BC, Canada, August 7, 2022

A Novel Low-Leakage ESD Power Clamp Circuit with Adjustable Transient Response Time.

Zilong Shen, Yize Wang, Xing Zhang, Yuan Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Data-Driven Robust Congestion Pricing.

Yize Wang, Dario Paccagnan

Proceedings of the 61st IEEE Conference on Decision and Control, 2022

2020

A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics.

Yize Wang, Guangyi Lu, Yuan Wang

IEEE Access, 2020

2019

Improved turn-on behavior in a diode-triggered silicon-controlled rectifier for high-speed electrostatic discharge protection.

Lizhong Zhang, Yuan Wang, Yize Wang, Xing Zhang, Yandong He

Sci. China Inf. Sci., 2019

2018

Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity.

Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness.

Yuan Wang, Guangyi Lu, Yize Wang, Xing Zhang

IEICE Trans. Electron., 2017

A novel TLP-based method to deliver IEC 61000-4-2 ESD stress.

Yize Wang, Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang

IEICE Electron. Express, 2017

Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process.

Guangyi Lu, Yuan Wang, Yize Wang, Xing Zhang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

A novel SPICE circuit model of electrostatic discharge (ESD) generator.

Jian Cao, Yize Wang, Yuan Wang, Guangyi Lu, Xing Zhang

IEICE Electron. Express, 2016