Yiyang Shu

Orcid: 0000-0002-6606-9057

According to our database1, Yiyang Shu authored at least 20 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
A Phase-Modulation Phase-Shifting Phased-Array Transmitter With Phase Self-Calibration and Deep PBOs Efficiency Enhancement.
IEEE J. Solid State Circuits, August, 2024

A Phased-Array Transceiver With 2-Dimension Continuously Auto Link-Tracking Operation and Time Division Modulator.
IEEE J. Solid State Circuits, August, 2024

A Fractional-N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD.
IEEE J. Solid State Circuits, August, 2024

A W-Band 2 × 2 Phased-Array Transmitter With Digital Gain-Compensation Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

2023
Scalable Inter-Core-Shaping Multi-Core Oscillator With Canceled Common-Mode Destructive Coupling and Robust Common-Mode Resonance.
IEEE J. Solid State Circuits, December, 2023

Millimeter-Wave Quadrature Mixed-Mode Transmitter With Distributed Parasitic Canceling and LO Leakage Self-Suppression.
IEEE J. Solid State Circuits, March, 2023

A 28GHz Scalable Inter-Core-Shaping Multi-Core Oscillator with DM/CM-Configured Coupling Achieving 193.3dBc/Hz FoM and 205.5dBc/Hz FoMA at 1MHz Offset.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 4.8dB NF, 70-to-86GHz Deep-Noise-Canceling LNA Using Asymmetric Compensation Transformer and 4-to-1 Hybrid-Phase Combiner in 40nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

An 8-Element 23-40 GHz Continuously Auto Link-Tracking Phased-Array Transceiver with Time Division Modulator Achieving 7μs Tracking Time, 25.3% TX System Efficiency, 800MHz-64QAM Modulation for 5G NR.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A 21.8-41.6GHz Fractional-N Sub-Sampling PLL with Dividerless Unequal-REF-Delay Frequency-Locked Loop Achieving -246.9dB FoMj and -270.3dB FoMj,N.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
A Phase-Modulation Phase-Shifting Phased-Array Transmitter with 10-Bit Fast-Locking Phase Self-Calibration and 0/2.5/6/12dB Power Back-Offs Efficiency Enhancement.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

22-30GHz Quadrature Hybrid SCPA with LO Leakage Self-Suppression and Distributed Parasitic-Cancelling Sub-PA Array for Linearity and Efficiency Enhancement.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

Watt-Level Triple-Mode Quadrature SFCPA with 56 Peaks for Ultra-Deep PBO Efficiency Enhancement Using IQ Intrinsic Interaction and Adaptive Phase Compensation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
A Cascaded Mode-Switching Sub-Sampling PLL With Quadrature Dual-Mode Voltage Waveform-Shaping Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A 2-D Mode-Switching Quad-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting.
IEEE J. Solid State Circuits, 2021

A Low Phase Noise and High FoM Distributed-Swing-Boosting Multi-Core Oscillator Using Harmonic-Impedance-Expanding Technique.
IEEE J. Solid State Circuits, 2021

20.2 A 3.09-to-4.04GHz Distributed-Boosting and Harmonic-Impedance-Expanding Multi-Core Oscillator with-138.9dBc/Hz at 1MHz Offset and 195.1dBc/Hz FoM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A 20-32-GHz Quadrature Digital Transmitter Using Synthesized Impedance Variation Compensation.
IEEE J. Solid State Circuits, 2020

17.4 A 18.6-to-40.1GHz 201.7dBc/Hz FoMT Multi-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020


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